1. Field of the Invention
The present invention relates to a method for generating an analysis model for analyzing power supply noise of a circuit board, a power supply noise analysis model generating apparatus, and a recording medium on which a program thereof is recorded.
2. Description of the Related Art
With an increase in the density of elements mounted on a circuit board, the density of an electric current of a power supply unit has been significantly growing. Additionally, the operating frequency of a circuit has been rising, and also a frequency component included in a power supply current has been increasing. The number of faults, which are not conventionally problematic and caused by power supply noise, has been growing due to such a situation.
Power supply noise is evaluated by creating a power supply noise analysis model of a circuit board, which copes with such faults, and by using a circuit simulator with the power supply noise analysis model.
Conventionally, a power supply noise analysis model is created by extracting as a power supply pair a portion where power supply islands existing in different power supply layers of a circuit board, by arranging nodes in units of power supply pairs, and by calculating impedance between nodes.
FIGS. 1A and 1B show a conventional power supply noise analysis model. A portion where power supply islands existing in different power supply layers overlap is extracted as a power supply pair. FIG. 1A shows a case where power supply pairs 1 and 2 are extracted from a first layer. 4 nodes represented with white circles shown in FIG. 1A are arranged in the power supply pair 1, and also 4 nodes represented with white circles are  arranged in the power supply pair 2.
FIG. 1B shows mesh regions that respectively enclose the nodes. A predetermined region centering each of the nodes is set as a mesh region.
If the power supply pairs extracted as described above are individually put into models, power supply pairs existing in the same power supply island are generated as separate models. Therefore, the power supply pairs 1 and 2 are merged into one model by setting boundary line nodes in a boundary line between these pairs as shown in FIG. 1A.
However, since the number of power supply pairs to be partitioned increases in a power supply island of a complicated shape, also the number of boundary line nodes grows. As a result, the ratio of the number of boundary line nodes, which occupies the total number of nodes, becomes high. As the number of boundary line nodes increases, so does the number of elements such as an inductor, a resistor, a capacitor, etc. of a power supply noise analysis model. This leads to an increase in the size of the power supply noise analysis model. Additionally, as the size of a power supply noise analysis model increases, analysis time at the time of simulation becomes longer.
Furthermore, a via is used to connect layers on a multi-layer circuit board. For example, if the angles of a via in an upper layer and a via in a lower layer do not align, misaligned portions become overlapping portions of a power supply island of another layer, and the overlapping portions are extracted as power supply pairs. Therefore, a plurality of minute power supply pairs is extracted for one via. If these pairs are respectively put into models, the number of power supply noise analysis models increases.
Still further, if an overlapping portion of power supply islands having shapes shown in FIG. 3 are extracted, for example, if the overlapping portion of graphics A and B is extracted, an intersection point T of the graphics A and B sometimes becomes an intersection point T′ due to an error of a graphic computation.  If an overlapping portion of the graphics A and C including this intersection point T′ is extracted as a power supply pair, a shaded region and a black region in FIG. 3 are extracted as separate overlapping regions, and the black region in FIG. 3 is extracted as a power supply pair. A minute power supply pair which does not originally exist is extracted due to an error of a graphic computation as described above, leading to an increase in the number of power supply noise analysis models.
FIGS. 4A and 4B explain a conventional method for calculating the inductance of a lead pattern. FIG. 4A is a perspective view of a circuit board, whereas FIG. 4B is its cross-sectional view.
If the lead pattern of a power supply island in an L1 layer, and a power supply island in an L9 layer configure a power supply pair, the inductance of the lead pattern in the L1 layer is conventionally calculated from the area of the lead pattern in the L1 layer, the area of the power supply island in the L9 layer, and a distance between the L1 and the L9 layers. However, if a power supply island exists in another layer in the neighborhood of the lead pattern as shown in FIG. 4A, the inductance calculated as described above differs from an actual value in many cases.
Patent Document 1 recites the creation of a semiconductor device model for a power supply noise analysis by creating each model of power supply wiring, an internal capacitance, an internal consumption current, and an input/output cell of a semiconductor device, and by merging the models.
Patent Document 2 recites a ripple process executed when the arrangement of nodes of a power supply noise analysis model is determined.
[Patent Document 1] Japanese Published Unexamined Patent Application No. 2004-234618
[Patent Document 2] Japanese Published Unexamined Patent Application No. 2004-334654 